Ultra-abrupt semiconductor junction profile

ABSTRACT

The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

CROSS REFERENCE TO RELATED APPLICATION

This is a Divisional Application of U.S. patent application Ser. No.11/694,936 filed on Mar. 30, 2007, presently pending, therein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a field of semiconductor integratedcircuit (IC) manufacturing, and more specifically, to an apparatus forand a method of forming an ultra-abrupt semiconductor junction profile.

2. Discussion of Related Art

Continual shrinking of a complementary metal-oxide-semiconductor (CMOS)integrated circuit (IC) as exemplified in the well-known Moore's Lawrequires a formation of an ultra-abrupt semiconductor junction. In acase of a PMOS transistor in the CMOS IC, a source/drain region and itsextension must have a very high Boron concentration with an extremelyabrupt Boron profile. In the analogous case of an NMOS transistor in theCMOS IC, the source/drain region and its extension must have a very highArsenic or Phosphorus concentration with an extremely abrupt Arsenicprofile.

A p+/n semiconductor junction may be formed by ion implanting a p-typedopant, such as Boron, into an n-type substrate, such as Arsenic-dopedSilicon, followed by annealing the substrate at over 1,000 degrees C.The NMOS transistor requires a high anneal temperature to activate thedopant. Unfortunately, the use of such a high temperature results in asignificant out-diffusion of the dopant into the substrate in the PMOStransistor.

Thus, a need exists for an apparatus of and a method of forming anultra-abrupt semiconductor junction profile.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a method of forming an ultra-abruptsemiconductor junction profile according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following description, numerous details, such as specificmaterials, dimensions, and processes, are set forth in order to providea thorough understanding of the present invention. However, one skilledin the art will realize that the invention may be practiced withoutthese particular details. In other instances, well-known semiconductorequipment and processes have not been described in particular detail soas to avoid obscuring the present invention.

The present invention describes an apparatus for and a method of formingan ultra-abrupt semiconductor junction profile in a device, such as atransistor. Ultra-abrupt refers to a very steep semiconductor junctionprofile.

In an embodiment of the present invention, a transistor may have a gatewith multiple surfaces, such as a trigate. In another embodiment of thepresent invention, the transistor may have multiple gates, such as amultiple-gate field effect transistor (MUGFET). For simplicity ofexposition, a transistor with a single gate is described in thefollowing disclosure.

First, a low energy ion implantation into a substrate, such as a wafer,may be used to adjust a threshold voltage, V_(t), of a channel region ofa transistor. In an embodiment of the present invention, the substratemay include a deep n-well or a deep p-well that is formed by a highenergy ion implantation. In another embodiment of the present invention,the substrate may include silicon-on-insulator (SOI).

In an embodiment of the present invention, the transistor may beseparated from another device by a shallow trench isolation (STI). Inanother embodiment of the present invention, the transistor formed inthe SOI is a fully-depleted transistor.

A gate dielectric stack may be formed over the channel region. The gatedielectric may have a physical thickness of 0.6-1.5 nm. In an embodimentof the present invention, the gate dielectric may include SiON. Inanother embodiment of the present invention, the gate may include ahigh-k (dielectric constant, k, such as greater than 15) material, suchas HfO₂.

A gate (electrode) may be formed over the gate dielectric. The gate mayhave a thickness of 40-65 nm. In an embodiment of the present invention,the gate may include doped polysilicon.

In another embodiment of the present invention, the gate may include ametal, such as Tantalum or Titanium for the NMOS transistor and TantalumNitride, Tungsten Nitride, or Titanium Nitride for the PMOS transistor.A barrier layer may be included at a certain interface to avoidinterdiffusion, prevent oxidation, or improve adhesion.

Lithography and etch may be used to form the gate having a certainwidth. The width refers to a distance between two facing sides of thegate. The width may correspond to a physical gate length of 25-50 nm. Inan embodiment of the present invention, an alternating phase-shiftingmask is used with deep ultraviolet (DUV) light to define the gate in achemically amplified photoresist. In another embodiment of the presentinvention, double patterning is used. The gate may be trimmed as neededto reduce the width.

During fabrication of the transistor, a raised source/drain may beformed adjacent to the two sides of the gate (electrode). First, arecess is etched (block 100 as shown in FIG. 1) in the regions adjacentto both sides of the gate of the transistor using the gate as an etchmask.

Next, a pre-amorphization implant (block 200), such as of Silicon orGermanium (Group IVA of the periodic table), may be performed into therecessed regions adjacent to both sides of the gate of the transistor.In an embodiment of the present invention, the pre-amorphization implant(PAI) is not performed into the recessed regions.

In an embodiment of the present invention, a Silicon pre-amorphizationimplant may have an energy of 5-15 keV. In another embodiment of thepresent invention, the Silicon preamorphization implant may have anenergy of 15-45 keV. The dose for the Silicon pre-amorphization implantmay be (0.4-2.5) E+15 atoms/cm².

In an embodiment of the present invention, a Germanium pre-amorphizationimplant may have an energy of 0.8-5 keV. In another embodiment of thepresent invention, the Germanium pre-amorphization implant may have anenergy of 5.0-30 keV. The dose for the Germanium pre-amorphizationimplant may be (0.5-3.0) E+15 atoms/cm².

In an embodiment of the present invention, a spike anneal (block 250) isperformed after the pre-amorphization implant and before one or moreco-implants of one or more species. In another embodiment of the presentinvention, no anneal is performed between the pre-amorphization implantand the one or more co-implants of the one or more species.

Then, the one or more co-implants (block 310, 320) of the one or morespecies may be performed into the recessed regions under optimalconditions according to an embodiment of the present invention.Parameters for the one or more co-implants that may require adjusting,controlling, or optimizing a tool (equipment) or a process may includeangle, energy, and dose. In a certain case, current (of the beam) mayalso be a critical parameter. In another case, an ionic species to beimplanted may further be a critical parameter since energy, dose, andcurrent may be affected by choice of a particular mass, charge, ormass-to-charge ratio.

Selection of an optimal angle for the ion implantation ensures a propercoverage for sidewall surfaces as well as a bottom surface of therecessed regions. An angled orientation refers to a tilt away from aperpendicular or normal incidence to an upper surface of the substrate.A 0-degree tilt away from the normal incidence corresponds to 90 degreesto the upper flat surface of the substrate.

In an embodiment of the present invention, an angled co-implant isperformed at an angle selected from a range of 5-15 degrees tilt awayfrom a normal incidence. In another embodiment of the present invention,the angled co-implant is performed at an angle selected from a range of15-25 degrees tilt away from the normal incidence. In still anotherembodiment of the present invention, the angled co-implant is performedat an angle selected from a range of 25-35 degrees tilt away from thenormal incidence. In yet another embodiment of the present invention,the co-implant is performed at several different angles to minimize anyshadowing and asymmetry that may otherwise result from performing animplant at an angle or a tilt.

In an embodiment of the present invention, a single co-implant of asingle species, such as Carbon (Group IVA of the periodic table), isperformed into the recessed regions adjacent to both sides of the gateof the transistor.

Selection of an optimal energy ensures a proper depth below the surfacefor nominal placement of the Carbon (in an as-implanted profile). TheCarbon should be located slightly deeper than the peak concentration ofthe subsequent Boron implant. In an embodiment of the present invention,the energy for the Carbon co-implant may be 1-3 keV. In anotherembodiment of the present invention, the energy for the Carbonco-implant may be 3-6 keV. In another embodiment of the presentinvention, the energy for the Carbon co-implant may be 6-10 keV.

Selection of an optimal dose (in 2 dimensions) to deliver the species,such as Carbon, to the substrate should ensure a proper concentration(in 3 dimensions) for nominal placement of the species, such as Carbon,(in an as-annealed profile). In an embodiment of the present invention,the dose for the Carbon co-implant may be (0.5-2.0) E+15 atoms/cm². Inan embodiment of the present invention, the peak concentration of Carbonmay be (1.0-4.0) E+19 atoms/cm³.

In some cases, selection of an optimal current may confer one or moreadvantages such as improving uniformity, reducing charging, minimizingheating, avoiding damage, decreasing diffusion, and increasingthroughput.

In an embodiment of the present invention, two or more co-implants oftwo or more species may be performed to customize a trapping zone forthe dopant, such as Boron. In an embodiment of the present invention,the co-implanted species may be substitutional while the implanteddopant may be interstitial. In another embodiment of the presentinvention, a co-implant of Fluorine (Group VIIA of the periodic table)is performed before a co-implant of Carbon (Group IVA of the periodictable). In another embodiment of the present invention, the Fluorineco-implant is performed after the Carbon co-implant.

In an embodiment of the present invention, the co-implant may beperformed in 2 steps with two different energies and two different dosesto place the implanted species, such as Carbon, both slightly above andslightly below the Boron to surround (sandwich) the Boron and prevent itfrom diffusing.

In an embodiment of the present invention, a spike anneal (block 350) isperformed after the one or more co-implants and before the filling ofthe recessed regions with Silicon-Germanium. In another embodiment ofthe present invention, no anneal is performed between the one or moreco-implants and the filling of the recessed regions, such as withSilicon-Germanium.

Next, the recessed regions adjacent to both sides of the gate(electrode) of the transistor may be filled (block 400). In anembodiment of the present invention, the recessed regions may be filledusing selective epitaxial deposition.

In an embodiment of the present invention, the recessed regions may befilled with Silicon-Germanium (Group IVA of the periodic table). A filmor layer of SiGe will enhance carrier mobility and thus improvetransistor performance. The Silicon-Germanium may be dopedintrinsically, such as during deposition, or extrinsically, such as withan implant.

In an embodiment of the present invention, the recessed regions may befilled to form a raised source/drain. In an embodiment of the presentinvention, the recessed regions may be overfilled to a desired thicknessor height.

In an embodiment of the present invention, a dopant may be used to dopea tip or source/drain extension (block 500) adjacent to both sides ofthe gate (electrode) of the transistor. In particular, Boron (Group IIIA of the periodic table) may be used to dope the tip or source/drainextension (SDE) in the PMOS transistor while Arsenic or Phosphorus(Group VA of the periodic table) may be used to dope the tip orsource/drain extension in the NMOS transistor. The tip or source/drainextension ion implant for Boron may have an energy of 200-750 eV and adose of (0.5-2.0) E+15 atoms/cm2. The tip or source/drain extension ionimplant for Phosphorus may have an energy of 400-1,500 eV and a dose of(2.5-9.0) E+14 atoms/cm².

The source/drain extension is shallow and may have a junction depth of10-20 nm. In an embodiment of the present invention, the tip orsource/drain extension may be formed with an ultra-low energy implant.The tip or source/drain implant may be an angled or tilted implant. Inan embodiment of the present invention, plasma or gas phase doping maybe used to form the tip or source/drain extension.

An anneal (block 550) is performed after an ion implantation to activatea dopant and to remove damage. The damage may include point defects andstresses in the substrate. In an embodiment of the present invention,the anneal is performed at a temperature selected from a range of980-1,030 degrees C. In another embodiment of the present invention, theanneal is performed at a temperature selected from a range of1,030-1,080 degrees C. In another embodiment of the present invention,the anneal is performed at a temperature selected from a range of1,080-1,130 degrees C.

Annealing for a very short duration helps to minimize diffusion ofdopant. In an embodiment of the present invention, the anneal is a spikeanneal. In another embodiment of the present invention, the anneal is arapid thermal anneal (RTA).

The Boron atom has a small size. Boron forms clusters interstitially anddiffuses through interstitial motion. Transient-enhanced diffusion (TED)of Boron results in fast diffusion.

According to an embodiment of the present invention, placing the Carbonslightly below (deeper than) the peak concentration of Boron willarrest, retard, or suppress the out-diffusion of Boron through the SiGeand into the adjacent or underlying substrate.

In another embodiment of the present invention, the Carbon may be placedboth slightly above (shallower than) and slightly below (deeper than)the peak concentration of the Boron to surround (sandwich) the Boron andprevent it from diffusing.

The substitutional Carbon acts as a trap for the Boron interstitials inthe SiGe. However, selecting a too low dose for the Carbon implant maynot confer sufficient benefit while selecting a too high dose for theCarbon implant may damage a structure of the substrate unnecessarily.

Out-diffusion refers to an excessive movement of a dopant away from anas-implanted (original) location due to a driving force such as aconcentration gradient or a thermal gradient. In an embodiment of thepresent invention, the out-diffusion of Boron in the PMOS transistorbeyond the original as-implanted depth should be 1.5-3.0 nm. In anotherembodiment of the present invention, the out-diffusion of Boron in thePMOS transistor beyond the original as-implanted depth should be 3.0-6.0nm.

An apparatus, structure, or device envisioned in various embodiments ofthe present invention may include a tip or source/drain extension havingan ultra-abrupt semiconductor junction profile. The ultra-abruptsemiconductor junction profile is formed due to a trapping of aninterstitial dopant, such as Boron, by a substitutional co-implantedspecies, such as Carbon.

In an embodiment of the present invention, the co-implanted species,such as Carbon, may be located slightly below (deeper than) the peakconcentration of the dopant, such as Boron, in the apparatus to blockthe Boron and prevent it from diffusing.

In another embodiment of the present invention, the co-implantedspecies, such as Carbon, may be located both slightly above (shallowerthan) and slightly below (deeper than) the peak concentration of thedopant, such as Boron, in the apparatus to surround (sandwich) the Boronand prevent it from diffusing.

In an embodiment of the present invention, the ultra-abruptsemiconductor junction profile in the apparatus may have a slope of 3-5nm/decade. In another embodiment of the present invention, theultra-abrupt semiconductor junction profile in the apparatus may have aslope of 5-7 nm/decade.

Secondary ion mass spectroscopy (SIMS) is a destructive analyticaltechnique that may be performed over a sufficiently large area of asample to determine a vertical profile of concentration as a function ofdepth. The profile may include a characteristic slope, peak, shoulder,and tail.

In an embodiment of the present invention, the Boron in the tip or thesource/drain extension of the PMOS transistor may have a peakconcentration of (0.7-3.0) E+20 atoms/cm³. In another embodiment of thepresent invention, the Boron may have a peak concentration of (0.3-1.2)E+21 atoms/cm³. In an embodiment of the present invention, the junctiondepth (X_(j)) may be 12-18 nm. In another embodiment of the presentinvention, the junction depth may be 18-27 nm.

In an embodiment of the present invention, the Phosphorus in the tip orthe source/drain extension of the NMOS transistor may have a peakconcentration of (0.6-5.0) E+20 atoms/cm³. In another embodiment of thepresent invention, the Phosphorus may have a peak concentration of(0.5-4.0) E+21 atoms/cm³. In an embodiment of the present invention, thejunction depth (X_(j)) may be 8-12 nm. In another embodiment of thepresent invention, the junction depth may be 12-18 nm.

Scanning spreading resistance microscopy (SSRM) is a technique that maybe used to determine a 2-dimensional profile of activated carrierconcentration.

Formation of an ultra-abrupt semiconductor junction profile will improveperformance (switching speed) of the transistor. A shallower junctiondepth may be achieved due to a decrease in vertical diffusion. Anoverlap capacitance (C_(ov)) between the gate (electrode) and thesource/drain extension may be reduced due to a decrease in lateraldiffusion. A source/drain (series) resistance may be reduced due toimproved dopant activation. A drive current (I_(on)) for a given drainvoltage may be increased due to improved dopant activation. Shortchannel effects (SCE) may be mitigated by improved dopant activation.

In an embodiment of the present invention, a halo implant is performedafter the tip or the source/drain extension implant. In anotherembodiment of the present invention, the halo implant is performedbefore the tip or the source/drain extension implant. Reversing thesequence of implants may further reduce diffusion of Boron.

Sidewall spacers may be formed by chemical vapor deposition along thetwo facing sides of the gate. The sidewall spacer may have a thicknessafter etch of 25-80 nm. In an embodiment of the present invention, thespacers may include two layers of dielectric material, including SiON.

The SiGe is heavily doped to form a raised source/drain using the gateand the sidewall spacers as a mask. An ultra-low energy ion implantationmay be used to dope the raised source/drain. Alternatively, plasma orgas phase doping may be used to dope the raised source/drain. The raisedsource/drain may have a junction depth of 20-40 nm.

In an embodiment of the present invention, the doped polysilicon gateand the source/drain may be capped with an overlying layer of NickelSilicide. The Nickel Silicide may have a thickness of 15-25 nm. In somecases, the gate may be fully silicided (FUSI). In another embodiment ofthe present invention, a metal gate may be used.

An interlayer dielectric (ILD) may be formed over the transistor. TheILD may be formed from a low-k (dielectric constant, k, such as 1.0-2.2)material that is formed by spin coating or chemical vapor deposition(CVD) of a material, such as organosilicate glass (OSG) or carbon-dopedoxide (CDO). The ILD may be porous and may include an air gap.

A dual Damascene scheme may be used to form multilayer interconnects tothe transistor with copper metal or alloy. As needed, diffusion barrierlayers and shunt layers may be included for the vias and metal lines ineach layer. Between 3 and 10 layers of interconnects may be formed.

Many embodiments and numerous details have been set forth above in orderto provide a thorough understanding of the present invention. Oneskilled in the art will appreciate that many of the features in oneembodiment are equally applicable to other embodiments. One skilled inthe art will also appreciate the ability to make various equivalentsubstitutions for those specific materials, processes, dimensions,concentrations, etc. described herein. It is to be understood that thedetailed description of the present invention should be taken asillustrative and not limiting, wherein the scope of the presentinvention should be determined by the claims that follow.

1. An apparatus comprising: providing a channel region in a substrate; agate dielectric disposed over said channel region; a gate disposed oversaid gate dielectric; recessed regions disposed adjacent to both sidesof said gate; a dopant disposed at a depth in said recessed regionsadjacent to both sides of said gate, said dopant comprising source-drainextensions; one or more co-implanted species disposed slightly belowsaid depth in said recessed regions; raised source/drain disposed insaid recessed regions; and sidewall spacers disposed along two facingsides of said gate;
 2. The apparatus of claim 1 wherein said one or moreco-implanted species are at an angle tilted away from a normalincidence.
 3. The apparatus of claim 1 further comprising said one ormore co-implanted species also disposed slightly above said depth insaid recessed regions.
 4. The apparatus of claim 1 wherein said dopantis interstitial.
 5. The apparatus of claim 1 wherein said dopantcomprises Boron.
 6. The apparatus of claim 1 wherein said one or moreco-implanted species is substitutional.
 7. The apparatus of claim 1wherein said one or more co-implanted species comprises Fluorineimplanted before Carbon.
 8. The apparatus of claim 1 further comprisinga pre-amorphization implant in said recessed regions.
 9. The apparatusof claim 9 wherein said pre-amorphization implant comprises Silicon orGermanium.
 10. The apparatus of claim 1 wherein said raised source/draincomprises Silicon Germanium filled into said recessed regions.
 11. Theapparatus of claim 1 further comprising a halo implant performed aftersaid source/drain extension implant.
 12. An apparatus comprising: asource/drain extension having an ultra-abrupt semiconductor junctionprofile, said ultra-abrupt semiconductor profile comprising aninterstitial dopant disposed slightly above one or more substitutionalco-implanted species.
 13. The apparatus of claim 15 comprising saidinterstitial dopant also disposed slightly below said one or moresubstitutional co-implanted species.
 14. The apparatus of claim 15wherein said interstitial dopant comprises Boron.
 15. The apparatus ofclaim 15 wherein said substitutional co-implanted species comprisesCarbon.
 16. The apparatus of claim 1 wherein said co-implanted speciesis substitutional.
 17. An apparatus comprising: a substrate; asource/drain extension disposed in said substrate; a dopant disposed insaid source/drain extension; and a co-implanted species disposedslightly below a peak concentration of said dopant.
 18. The apparatus ofclaim 17 wherein said co-implanted species is Carbon or Fluorine. 19.The apparatus of claim 17 further comprising said co-implanted speciesalso disposed slightly above said peak concentration of said dopant. 20.The apparatus of claim 17 wherein said source/drain extension comprisesan ultra-abrupt semiconductor junction profile.